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PLDASM.#10
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1995-04-10
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:PLDasm_LANGUAGE_SUMMARY
:SIGNAL_EXTENSIONS
:Macrocell_Output_Signal_Extensions
~.FB~ - feedback multiplexer output
~.IO~ - I/O pin feedback
:Macrocell_Output_Control_Signal_Extensions
~.TRST~ - tristate enable/disable control input
:Flip-Flop_Clock_Signal_Extensions
~.ACLK~ - asynchronous clock input
~.CLKF~ - synchronous clock input
~.ALE~ - asynchronous latch enable input
~.LE~ - synchronous latch enable input
:Flip-Flop_Data_Signal_Extensions
~.D~ - D flip-flop data input
~.J~ - JK flip-flop data input
~.K~ - JK flip-flop data input
~.R~ - SR flip-flop data input
~.S~ - SR flip-flop data input
~.T~ - toggle flip-flop data input
:Flip-Flop_Control_Signal_Extensions
~.RSTF~ - flip-flop reset control input
~.SETF~ - flip-flop set control input
:State_Machine_Output_Signal_Extensions
~.OUTF~ - Mealy/Moore machine output
:RAM_Data_Signal_Extensions
~.ADDR~ - SRAM address line
~.DATA~ - SRAM data output
:RAM_Control_Signal_Extensions
~.BE~ - SRAM block enable
~.WE~ - SRAM write enable
:Comparator_Signal_Extensions
~.CMP~ - 12-bit comparator output
:PLDasm_KEYWORDS
:Design_Header_Keywords
~TITLE~ - specify design's title
~AUTHOR~ - specify designer
~COMPANY~ - specify designer's company
~DATE~ - specify date of design
~REVISION~ - specify design's revision #
~PATTERN~ - specify identifying pattern
:Design_Tracking_Keywords
~SIGNATURE~ - load identifying pattern
:OPTIONS_Keywords
~OPTIONS~ - chip options follow
~TURBO~ - fast/slow enable/disable
~SECURITY~ - config. readback enable/disable
:CHIP_Declaration_Keywords
~CHIP~ - specify type of FPGA or PLD
~IFX780_84~ - EPX780 FPGA in 84-pin PLCC
~IFX780_132~ - EPX780 FPGA in 132-pin PQFP
~IFX8160_208~ - EPX8160 FPGA in 208-pin PQFP
~INTEL_ARCH~ - device-independent architecture
:Pin_Declaration_Keywords
~PIN~ - pin declaration
~NODE~ - buried macrocell declaration
~INPUT~ - input-only pin
~CMOS_LEVEL~ - CMOS input thresholds
~TTL_LEVEL~ - TTL input thresholds
~OUTPUT~ - output-only pin
~3VOLT~ - 3.3V output signal range
~5VOLT~ - 5V output signal range
~OPEN_DRAIN~ - output pulls to ground only
~HIGH~ - active high output
~LOW~ - active low output
~COMB~ - combinatorial output
~COMBINATORIAL~
~REG~ - registered output
~REGISTERED~
~LAT~ - latched output
~LATCHED~
~REGFBK~ - registered feedback
~CMBFBK~ - combinatorial feedback
~LATFBK~ - latched feedback
~TREGFBK~ - toggle flip-flop feedback
~PINFBK~ - feedback signal going to pin
~DELAYCLK~ - dlyd. sync. clock to flip-flop
~RAM~ - SRAM block input/output
:RAM_Initialization_Keywords
~DEFAULT_VALUE~ - entire RAM initial value
~RAM_DEFAULTS~ - RAM location initial values
:Design_Section_Keywords
~EQUATIONS~ - start Boolean equations
~T_TAB~ - start truth-table
~STATE~ - start state machine description
:Logic_Level_Keywords
~GND~ - logic low
~VCC~ - logic high
~NC~ - no connection
:Boolean_Equation_Keywords
~/~ - NOT
~*~ - AND
~+~ - OR
~:+:~ - XOR
~= ~ - combinatorial assignment
~:=~ - registered assignment
~*=~ - latched assignment
:State_Machine_Keywords
~MOORE_MACHINE~ - Moore state machine
~MEALY_MACHINE~ - Mealy state machine
~CONDITIONS~ - state transition conditions
~DEFAULT_BRANCH~ - default state transition
~NEXT_STATE~ - go to next state on default
~HOLD_STATE~ - hold state on default
~DEFAULT_OUTPUT~ - specify default outputs
~OUTPUT_HOLD~ - hold current outputs on default
:Hierarchical_Module_Keywords
~DEFMOD~ - begin module definition
~ENDMOD~ - end module definition
~FILE~ - specify file where module is defined
~MODULE~ - specify module to instantiate in design
:Simulation_Keywords
~SIMULATION~ - start simulation section
~VECTOR~ - group signals into a vector
~TRACE_OFF~ - trace the listed signal values
~TRACE_ON~ - stop tracing signal values
~PRLDF~ - initialize flip-flop values
~SETF~ - set signal values
~CLOCKF~ - toggle signal value twice
~IF~ - conditional execution
~THEN~ - terminates IF condition
~ELSE~ - alternate conditional action
~FOR~ - iterative loop
~TO~ - specify loop terminal value
~DO~ - terminate FOR setup
~WHILE~ - conditional loop
~BEGIN~ - begin block of statements
~END~ - end block of statements
~CHECK~ - compare signal to its correct value
:Simulation_Number_Representations
~HEXADECIMAL~ - 0x17FC or #H3A6D (leading 0x or #H)
~OCTAL~ - 0326 or #O174 (leading 0 or #O)
~BINARY~ - #B11010001 (leading #B)
~DECIMAL~ - 75 (no leading character sequence)
:Simulation_Conditionals
~=~ - equals (lowest precedence)
~/=~ - not equal
~>=~ - greater than or equal
~>~ - greater than
~<=~ - less than or equal
~<~ - less than (highest precedence)
**************************************
* Copyright 1995 by XESS Corporation *
* 2608 Sweetgum Drive *
* Apex, NC 27502 *
* USA *
* (919) 387-0076 *
* (800) 549-9377 *
**************************************